A magnetic random access memory (MRAM) is a non-volatile memory device that uses a magnetoresistance effect such that resistance of an electric conductor is changed in response to a circumferential magnetic field to thereby store information. An MRAM may include a plurality of MRAM cells with each MRAM cell including a magnetic tunnel junction (MTJ) on a single transistor.
An MTJ may include multiple thin layers such that electrons may tunnel through a very thin insulating layer sandwiched between two ferromagnetic electrodes when an external electrical signal is applied. A top electrode may be referred to as a free layer and a bottom electrode may be referred to as a pinned layer.
When magnetization directions within the free layer and the pinned layer are arranged parallel with respect to each other, a tunneling current flowing through the MTJ may have a relatively high value, and, the tunneling resistance may have a relatively low value. In contrast, when the magnetization directions within the free layer and the pinned layer are arranged anti-parallel with respect to each other, a tunneling current flowing through the MTJ may have a reduced value, and a tunneling resistance may have a relatively high value.
An MRAM may use magnetic charges to store information while a conventional memory may use electrical charges. Digital data represented as “0” and “1” may thus be differentiated to store a low resistance state where the magnetization directions of the two electrodes are parallel with respect to each other and a high resistance state where the magnetization directions are anti-parallel with respect to each other.
An anti-ferromagnetic layer which may be referred to as a pinning layer may be added to the pinned layer. The pinning layer may serve to fix the magnetization direction of the pinned layer. More particularly, the pinned layer attached to the pinning layer may have a relatively large switching field, and the magnetization direction of the pinned layer may be fixed always in a same direction when an applied magnetic field is smaller than the switching field. Thus, data of the MRAM cell may be determined by the magnetization direction within the free layer. The magnetization direction of the free layer may be changed by applying a magnetic field to its circumference. To change the magnetization direction of the free layer to a desired direction, conductive layers such as a bit line and a digit line may be formed to be orthogonal with respect to each other above/below the MTJ, and a current may flow through each conductive layer. A magnetic field induced by the current may be used to change the magnetization direction.
In this case, when the magnetization direction of an MTJ selected to store data is changed, a magnetization direction of an MTJ which is not selected should not be changed. To enhance integration density within a limited space, however, not only the size of each MTJ but also spaces between MTJs should be reduced. As a result of reductions in space between MTJs, a magnetic field which is generated to change a magnetization direction of a selected MTJ may increasingly affect adjacent MTJs which are not selected. If this effect becomes sufficient to invert a magnetization direction of adjacent MTJs, it may not be possible to perform a normal data storage operation.
To cope with the above-mentioned problems, alternate writing methods referred to as toggle switching have been proposed. A writing method for MRAMs using toggle switching is disclosed in U.S. Pat. No. 6,545,906 entitled “Method of writing to scalable magnetoresistance random access memory element “to Savtchenko et al. The disclosure of U.S. Pat. No. 6,545,906 is hereby incorporated herein in its entirety by reference.
According to U.S. Pat. No. 6,545,906, a digit line may be provided above a predetermined region of a semiconductor substrate. A bit line may be disposed on the digit line and may cross the digit line. An MTJ may be interposed at an intersection of the digit line and the bit line. The MTJ may include a second magnetic region, a tunneling barrier, and a first magnetic region which are sequentially stacked. Each of the first and second magnetic regions may include a synthetic anti-ferromagnetic (SAF) structure. The SAF structure may be formed of a top ferromagnetic layer, a bottom ferromagnetic layer, and an anti-ferromagnetic coupling spacer layer interposed therebetween.
FIG. 1 is a switching characteristic diagram of an MRAM cell fabricated as discussed in with U.S. Pat. No. 6,545,906.
Referring to FIG. 1, the horizontal axis indicates a magnetic field (Hw) induced on the bit line measured in units of Oersted (Oe) which is a unit of magnetoresistance and which is proportional to the magnitude of the bit line current. The longitudinal axis indicates a magnetic field (Hw) induced on the digit line also measured in units of Oersted (Oe). There are three regions in the switching characteristic diagram, i.e., a no switching region 92, a direct switching region 95, and a toggle switching region 97.
A method of writing using toggle switching region 97 may begin with reading an initial state of the MTJ. For example, in the case that the initial state of the MTJ is read as “1”, when a bit line positive current pulse is applied to the bit line and a digit line positive current pulse is applied to the digit line, a magnetization direction of the MTJ may be changed to write a “0” state. Next, when the bit line positive current pulse is applied again to the bit line and the digit line positive current pulse is applied again to the digit line, the magnetization direction of the MTJ may also be changed to write a “1” state. In this case, the bit line positive current pulse and the digit line positive current pulse may be applied with a time delay, but, these pluses may include a sequence which has an overlapped region therebetween. In addition, the magnitude of the current pulse may correspond to the toggle switching region 97.
The toggle switching region 97 may have a large switching region as shown in FIG. 1, but it may require a relatively high switching current. The relatively high switching current may in turn cause an undesirable increase in power consumption.